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122 lines
5.6 KiB
Plaintext
122 lines
5.6 KiB
Plaintext
;********************************************************************************************************
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; uC/CPU
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; CPU CONFIGURATION & PORT LAYER
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;
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; (c) Copyright 2004-2007; Micrium, Inc.; Weston, FL
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;
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; All rights reserved. Protected by international copyright laws.
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;
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; uC/CPU is provided in source form for FREE evaluation, for educational
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; use or peaceful research. If you plan on using uC/CPU in a commercial
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; product you need to contact Micrium to properly license its use in your
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; product. We provide ALL the source code for your convenience and to
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; help you experience uC/CPU. The fact that the source code is provided
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; does NOT mean that you can use it without paying a licensing fee.
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;
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; Knowledge of the source code may NOT be used to develop a similar product.
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;
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; Please help us continue to provide the Embedded community with the finest
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; software available. Your honesty is greatly appreciated.
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;********************************************************************************************************
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;********************************************************************************************************
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;
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; CPU PORT FILE
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;
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; ARM
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; IAR C Compiler
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;
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; Filename : cpu_a.s
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; Version : V1.17
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; Programmer(s) : JJL
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; JDH
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; ITJ
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;********************************************************************************************************
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;********************************************************************************************************
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; PUBLIC FUNCTIONS
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;********************************************************************************************************
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PUBLIC CPU_SR_Save
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PUBLIC CPU_SR_Restore
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;********************************************************************************************************
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; EQUATES
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;********************************************************************************************************
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CPU_ARM_CTRL_INT_DIS EQU 0xC0 ; Disable both FIQ & IRQ
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;********************************************************************************************************
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; CODE GENERATION DIRECTIVES
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;********************************************************************************************************
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RSEG CODE:CODE:NOROOT(2)
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CODE32
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;$PAGE
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;********************************************************************************************************
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; CRITICAL SECTION FUNCTIONS
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;
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; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
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; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
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; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
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; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
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;
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; Prototypes : CPU_SR CPU_SR_Save (void);
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; void CPU_SR_Restore(CPU_SR cpu_sr);
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;
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; Note(s) : (1) These functions are used in general like this :
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;
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; void Task (void *p_arg)
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; {
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; /* Allocate storage for CPU status register */
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; #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
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; CPU_SR cpu_sr;
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; #endif
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;
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; :
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; :
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; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
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; :
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; :
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; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
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; :
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; :
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; }
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;
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; (2) CPU_SR_Restore() is implemented as recommended by Atmel's application note :
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;
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; "Disabling Interrupts at Processor Level"
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;********************************************************************************************************
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CPU_SR_Save
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MRS R0, CPSR
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CPU_SR_Save_Loop
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; Set IRQ & FIQ bits in CPSR to DISABLE all interrupts
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ORR R1, R0, #CPU_ARM_CTRL_INT_DIS
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MSR CPSR_c, R1
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MRS R1, CPSR ; Confirm that CPSR contains the proper interrupt disable flags
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AND R1, R1, #CPU_ARM_CTRL_INT_DIS
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CMP R1, #CPU_ARM_CTRL_INT_DIS
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BNE CPU_SR_Save_Loop ; NOT properly DISABLED (try again)
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BX LR ; DISABLED, return the original CPSR contents in R0
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CPU_SR_Restore ; See Note #2
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MSR CPSR_c, R0
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BX LR
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;$PAGE
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;********************************************************************************************************
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; CPU ASSEMBLY PORT FILE END
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;********************************************************************************************************
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END
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