mirror of
https://github.com/dimoniche/solarium.vlad.git
synced 2026-01-30 04:53:30 +03:00
872 lines
30 KiB
C
872 lines
30 KiB
C
#include "rfid-spi.h"
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uid_struct uid; // Used by picc_read_card_serial().
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uid_struct * get_uid()
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{
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return &uid;
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}
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/**
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* Writes a number of bytes to the specified register in the MFRC522 chip.
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* The interface is described in the datasheet section 8.1.2.
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*/
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void
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write_bytes_mfrc522( pcd_register reg, uint8_t count, uint8_t *values)
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{
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spi_getSem();
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spi_selectChip(MFRC522_SPI);
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SpiExchange(MFRC522_SPI, (reg << 1) & 0x7e);
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uint8_t index;
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for (index = 0; index < count; index++)
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{
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SpiExchange(MFRC522_SPI, values[index]);
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}
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spi_unselectChip(MFRC522_SPI);
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spi_freeSem();
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} // End PCD_WriteRegister()
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/**
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* Writes a byte to the specified register in the MFRC522 chip.
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* The interface is described in the datasheet section 8.1.2.
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*/
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void
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write_mfrc522(uint8_t adr, uint8_t val)
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{
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spi_getSem();
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spi_selectChip(MFRC522_SPI);
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SpiExchange(MFRC522_SPI, (adr << 1) & 0x7e);
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SpiExchange(MFRC522_SPI, val);
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spi_unselectChip(MFRC522_SPI);
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spi_freeSem();
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}
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/**
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* Reads a byte from the specified register in the MFRC522 chip.
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* The interface is described in the datasheet section 8.1.2.
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*/
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uint8_t
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read_mfrc522(uint8_t dev_cmd)
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{
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uint8_t ret = 0x0;
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spi_getSem();
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spi_selectChip(MFRC522_SPI);
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SpiExchange(MFRC522_SPI, ((dev_cmd << 1) & 0x7e) | 0x80);
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ret = SpiExchange(MFRC522_SPI, 0x00);
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spi_unselectChip(MFRC522_SPI);
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spi_freeSem();
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return ret;
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}
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/**
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* Reads a number of bytes from the specified register in the MFRC522 chip.
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* The interface is described in the datasheet section 8.1.2.
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*/
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void read_fifo_mfrc522( pcd_register reg, uint8_t count, uint8_t *values, uint8_t rx_align)
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{
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if (count == 0)
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{
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return;
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}
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//Serial.print(F("Reading ")); Serial.print(count); Serial.println(F(" bytes from register."));
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uint8_t index = 0; // Index in values array.
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uint8_t ret = 0;
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uint8_t address = ((reg << 1) & 0x7e) | 0x80;
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spi_getSem();
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spi_selectChip(MFRC522_SPI);
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count--; // One read is performed outside of the loop
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SpiExchange(MFRC522_SPI, address);
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if (rx_align) { // Only update bit positions rx_align..7 in values[0]
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// Create bit mask for bit positions rx_align..7
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uint8_t mask = (0xFF << rx_align) & 0xFF;
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// Read value and tell that we want to read the same address again.
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uint8_t value;
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ret = SpiExchange(MFRC522_SPI, address);
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value=ret;
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// Apply mask to both current value of values[0] and the new data in value.
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values[0] = (values[0] & ~mask) | (value & mask);
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index++;
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}
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while (index < count) {
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ret = SpiExchange(MFRC522_SPI, address);
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values[index] = ret; // Read value and tell that we want to read the same address again.
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index++;
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}
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ret = SpiExchange(MFRC522_SPI, 0);
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values[index] = ret; // Read value and tell that we want to read the same address again.
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spi_unselectChip(MFRC522_SPI); // Release slave again
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spi_freeSem();
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} // End PCD_ReadRegister()
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/**
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* Translates the SAK (Select Acknowledge) to a PICC type.
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*
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* @return PICC_Type
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*/
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picc_type
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picc_get_type(uint8_t sak)
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{
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// http://www.nxp.com/documents/application_note/AN10833.pdf
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// 3.2 Coding of Select Acknowledge (SAK)
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// ignore 8-bit (iso14443 starts with LSBit = bit 1)
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// fixes wrong type for manufacturer Infineon (http://nfc-tools.org/index.php?title=ISO14443A)
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sak &= 0x7F;
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switch (sak)
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{
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case 0x04: return PICC_TYPE_NOT_COMPLETE; // uid_struct not complete
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case 0x09: return PICC_TYPE_MIFARE_MINI;
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case 0x08: return PICC_TYPE_MIFARE_1K;
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case 0x18: return PICC_TYPE_MIFARE_4K;
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case 0x00: return PICC_TYPE_MIFARE_UL;
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case 0x10:
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case 0x11: return PICC_TYPE_MIFARE_PLUS;
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case 0x01: return PICC_TYPE_TNP3XXX;
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case 0x20: return PICC_TYPE_ISO_14443_4;
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case 0x40: return PICC_TYPE_ISO_18092;
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default: return PICC_TYPE_UNKNOWN;
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}
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} // End picc_get_type()
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/**
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* Sets the bits given in mask in register reg.
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*/
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void
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pcd_set_register_bit_mask(pcd_register reg, uint8_t mask)
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{
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uint8_t tmp;
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tmp = read_mfrc522(reg);
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write_mfrc522(reg, tmp | mask); // set bit mask
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} // End pcd_set_register_bit_mask()
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/**
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* Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
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*
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* @return STATUS_OK on success, STATUS_??? otherwise.
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*/
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status_code
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pcd_calculate_crc(uint8_t *data, uint8_t length, uint8_t *result)
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{
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write_mfrc522(CommandReg, PCD_Idle); // Stop any active command.
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write_mfrc522(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
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write_mfrc522(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
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write_bytes_mfrc522(FIFODataReg, length, data); // Write data to the FIFO
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write_mfrc522(CommandReg, PCD_CalcCRC); // Start the calculation
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// Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73μs.
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// TODO check/modify for other architectures than Arduino Uno 16bit
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// Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
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uint16_t i;
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for ( i = 89; i > 0; i--)
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{
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// DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
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uint8_t n = read_mfrc522(DivIrqReg);
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if (n & 0x04)
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{ // CRCIRq bit set - calculation done
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write_mfrc522(CommandReg, PCD_Idle); // Stop calculating CRC for new content in the FIFO.
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// Transfer the result from the registers to the result buffer
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result[0] = read_mfrc522(CRCResultRegL);
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result[1] = read_mfrc522(CRCResultRegH);
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return STATUS_OK;
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}
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OSTimeDly(1);
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}
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// 89ms passed and nothing happend. Communication with the MFRC522 might be down.
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//printf("89ms passed and nothing happend.\n");
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return STATUS_TIMEOUT;
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} // End pcd_calculate_crc()
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/**
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* Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
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*/
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void
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pcd_reset()
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{
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write_mfrc522(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
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// The datasheet does not mention how long the SoftRest command takes to complete.
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// But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
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// Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74μs. Let us be generous: 50ms.
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//BUSYWAIT_UNTIL_ABS(RTIMER_NOW(), US_TO_RTIMERTICKS(1000));
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// Wait for the PowerDown bit in CommandReg to be cleared
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uint8_t count = 0;
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do {
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// Wait for the PowerDown bit in CommandReg to be cleared (max 3x50ms)
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us_delay_spi(50000);
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} while ((read_mfrc522(CommandReg) & (1 << 4)) && (++count) < 3);
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} // End pcd_reset()
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/**
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* Transfers data to the MFRC522 FIFO, executes a command, waits for completion and transfers data back from the FIFO.
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* CRC validation can only be done if back_data and back_len are specified.
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*
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* @return STATUS_OK on success, STATUS_??? otherwise.
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*/
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status_code
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pcd_communicate_tith_picc(uint8_t command, uint8_t wait_irq, uint8_t *send_data, uint8_t send_len, uint8_t *back_data, uint8_t *back_len, uint8_t *valid_bits, uint8_t rx_align, bool check_crc)
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{
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// Prepare values for BitFramingReg
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uint8_t txLastBits = valid_bits ? *valid_bits : 0;
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uint8_t bitFraming = (rx_align << 4) + txLastBits; // rx_align = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
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write_mfrc522(CommandReg, PCD_Idle); // Stop any active command.
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write_mfrc522(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
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write_mfrc522(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
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write_bytes_mfrc522(FIFODataReg, send_len, send_data); // Write send_data to the FIFO
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write_mfrc522(BitFramingReg, bitFraming); // Bit adjustments
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write_mfrc522(CommandReg, command); // Execute the command
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if (command == PCD_Transceive)
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{
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pcd_set_register_bit_mask(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
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}
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// Wait for the command to complete.
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// In pcd_initialization() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
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// Each iteration of the do-while-loop takes 17.86μs.
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// TODO check/modify for other architectures than Arduino Uno 16bit
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uint16_t i;
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for (i = 36; i > 0; i--)
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{
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uint8_t n = read_mfrc522(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
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if (n & wait_irq)
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{ // One of the that signal success has been set.
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break;
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}
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if (n & 0x01)
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{ // Timer interrupt - nothing received in 25ms
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return STATUS_TIMEOUT;
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}
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OSTimeDly(1);
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}
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// 35.7ms and nothing happend. Communication with the MFRC522 might be down.
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if (i == 0)
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{
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return STATUS_TIMEOUT;
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}
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// Stop now if any errors except collisions were detected.
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uint8_t errorRegValue = read_mfrc522(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
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if (errorRegValue & 0x13)
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{ // BufferOvfl ParityErr ProtocolErr
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return STATUS_ERROR;
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}
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uint8_t _valid_bits = 0;
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// If the caller wants data back, get it from the MFRC522.
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if (back_data && back_len)
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{
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uint8_t n = read_mfrc522(FIFOLevelReg); // Number of bytes in the FIFO
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if (n > *back_len)
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{
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return STATUS_NO_ROOM;
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}
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*back_len = n; // Number of bytes returned
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read_fifo_mfrc522(FIFODataReg, n, back_data, rx_align); // Get received data from FIFO
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_valid_bits = read_mfrc522(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
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if (valid_bits)
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{
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*valid_bits = _valid_bits;
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//printf(" *valid_bits = %x _valid_bits = %x\n",*valid_bits, _valid_bits);
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}
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}
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// Tell about collisions
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if (errorRegValue & 0x08)
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{ // CollErr
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return STATUS_COLLISION;
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}
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// Perform CRC_A validation if requested.
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if (back_data && back_len && check_crc)
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{
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// In this case a MIFARE Classic NAK is not OK.
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if (*back_len == 1 && _valid_bits == 4)
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{
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return STATUS_MIFARE_NACK;
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}
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// We need at least the CRC_A value and all 8 bits of the last byte must be received.
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if (*back_len < 2 || _valid_bits != 0)
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{
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return STATUS_CRC_WRONG;
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}
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// Verify CRC_A - do our own calculation and store the control in controlBuffer.
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uint8_t controlBuffer[2];
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status_code status = pcd_calculate_crc(&back_data[0], *back_len - 2, &controlBuffer[0]);
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if (status != STATUS_OK)
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{
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return status;
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}
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if ((back_data[*back_len - 2] != controlBuffer[0]) || (back_data[*back_len - 1] != controlBuffer[1]))
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{
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return STATUS_CRC_WRONG;
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}
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}
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return STATUS_OK;
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} // End pcd_communicate_tith_picc()
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/////////////////////////////////////////////////////////////////////////////////////
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// Functions for communicating with PICCs
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/////////////////////////////////////////////////////////////////////////////////////
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/**
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* Executes the Transceive command.
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* CRC validation can only be done if back_data and back_len are specified.
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*
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* @return STATUS_OK on success, STATUS_??? otherwise.
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*/
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status_code
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pcd_transceive_data(uint8_t *send_data, uint8_t send_len, uint8_t *back_data, uint8_t *back_len, uint8_t *valid_bits, uint8_t rx_align, bool check_crc)
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{
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uint8_t wait_irq = 0x30; // RxIRq and IdleIRq
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status_code result = (status_code)pcd_communicate_tith_picc(PCD_Transceive, wait_irq, send_data, send_len, back_data, back_len, valid_bits, rx_align, check_crc);
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return result;
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} // End pcd_transceive_data()
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/**
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* Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
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*
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* For MIFARE Classic the sector containing the block must be authenticated before calling this function.
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*
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* For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
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* The MF0ICU1 returns a NAK for higher addresses.
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* The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
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* For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
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* A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
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*
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* The buffer must be at least 18 bytes because a CRC_A is also returned.
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* Checks the CRC_A before returning STATUS_OK.
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*
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* @return STATUS_OK on success, STATUS_??? otherwise.
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*/
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status_code
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mifare_read( uint8_t blockAddr,uint8_t *buffer,uint8_t *bufferSize)
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{
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status_code result;
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// Sanity check
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if (buffer == NULL || *bufferSize < 18)
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{
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return STATUS_NO_ROOM;
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}
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// Build command buffer
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buffer[0] = PICC_CMD_MF_READ;
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buffer[1] = blockAddr;
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// Calculate CRC_A
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result = pcd_calculate_crc(buffer, 2, &buffer[2]);
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if (result != STATUS_OK)
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{
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return result;
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}
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// Transmit the buffer and receive the response, validate CRC_A.
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return pcd_transceive_data(buffer, 4, buffer, bufferSize, NULL, 0, true);
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} // End mifare_read()
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/**
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* Clears the bits given in mask from register reg.
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*/
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void
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pcd_clear_register_bit_mask(pcd_register reg, uint8_t mask)
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{
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uint8_t tmp;
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tmp = read_mfrc522(reg);
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write_mfrc522(reg, tmp & (~mask)); // clear bit mask
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} // End pcd_clear_register_bit_mask()
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/**
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* Used to exit the PCD from its authenticated state.
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* Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
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*/
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void
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pcd_stop_cryptol()
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{
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// Clear MFCrypto1On bit
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pcd_clear_register_bit_mask(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
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} // End pcd_stop_cryptol()
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status_code
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picc_select( uid_struct *uid, uint8_t valid_bits)
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{
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bool uidComplete;
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bool selectDone;
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bool use_cascade_tag;
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uint8_t cascadeLevel = 1;
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uint8_t count;
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uint8_t index;
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uint8_t uid_index; // The first index in uid->uidByte[] that is used in the current Cascade Level.
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int8_t current_level_known_bits; // The number of known uid_struct bits in the current Cascade Level.
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uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
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uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
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uint8_t rx_align; // Used in BitFramingReg. Defines the bit position for the first bit received.
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uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
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uint8_t *responseBuffer;
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uint8_t responseLength;
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status_code result;
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// Description of buffer structure:
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// Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
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// Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
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// Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
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// Byte 3: UID-data
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// Byte 4: UID-data
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// Byte 5: UID-data
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// Byte 6: BCC Block Check Character - XOR of bytes 2-5
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// Byte 7: CRC_A
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// Byte 8: CRC_A
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// The BCC and CRC_A are only transmitted if we know all the uid_struct bits of the current Cascade Level.
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//
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// Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: uid_struct contents and cascade levels)
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// uid_struct size Cascade level Byte2 Byte3 Byte4 Byte5
|
|
// ======== ============= ===== ===== ===== =====
|
|
// 4 bytes 1 uid0 uid1 uid2 uid3
|
|
// 7 bytes 1 CT uid0 uid1 uid2
|
|
// 2 uid3 uid4 uid5 uid6
|
|
// 10 bytes 1 CT uid0 uid1 uid2
|
|
// 2 CT uid3 uid4 uid5
|
|
// 3 uid6 uid7 uid8 uid9
|
|
|
|
// Sanity checks
|
|
if (valid_bits > 80)
|
|
{
|
|
return STATUS_INVALID;
|
|
}
|
|
|
|
// Prepare MFRC522
|
|
pcd_clear_register_bit_mask(CollReg, 0x80); // ValuesAfterColl=1 => Bits received after collision are cleared.
|
|
// Repeat Cascade Level loop until we have a complete UID.
|
|
uidComplete = false;
|
|
while (!uidComplete)
|
|
{
|
|
// Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
|
|
switch (cascadeLevel)
|
|
{
|
|
case 1:
|
|
buffer[0] = PICC_CMD_SEL_CL1;
|
|
uid_index = 0;
|
|
use_cascade_tag = valid_bits && uid->size > 4; // When we know that the uid_struct has more than 4 bytes
|
|
break;
|
|
case 2:
|
|
buffer[0] = PICC_CMD_SEL_CL2;
|
|
uid_index = 3;
|
|
use_cascade_tag = valid_bits && uid->size > 7; // When we know that the uid_struct has more than 7 bytes
|
|
break;
|
|
case 3:
|
|
buffer[0] = PICC_CMD_SEL_CL3;
|
|
uid_index = 6;
|
|
use_cascade_tag = false; // Never used in CL3.
|
|
break;
|
|
default:
|
|
//printf("INTERNAL ERROR");
|
|
return STATUS_INTERNAL_ERROR;
|
|
break;
|
|
}
|
|
|
|
// How many uid_struct bits are known in this Cascade Level?
|
|
current_level_known_bits = valid_bits - (8 * uid_index);
|
|
if (current_level_known_bits < 0)
|
|
{
|
|
current_level_known_bits = 0;
|
|
}
|
|
// Copy the known bits from uid->uidByte[] to buffer[]
|
|
index = 2; // destination index in buffer[]
|
|
if (use_cascade_tag)
|
|
{
|
|
buffer[index++] = PICC_CMD_CT;
|
|
}
|
|
uint8_t bytes_to_copy = current_level_known_bits / 8 + (current_level_known_bits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
|
|
if (bytes_to_copy)
|
|
{
|
|
uint8_t maxBytes = use_cascade_tag ? 3 : 4; // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
|
|
if (bytes_to_copy > maxBytes)
|
|
{
|
|
bytes_to_copy = maxBytes;
|
|
}
|
|
for (count = 0; count < bytes_to_copy; count++) {
|
|
buffer[index++] = uid->uidByte[uid_index + count];
|
|
}
|
|
}
|
|
// Now that the data has been copied we need to include the 8 bits in CT in current_level_known_bits
|
|
if (use_cascade_tag)
|
|
{
|
|
current_level_known_bits += 8;
|
|
}
|
|
|
|
// Repeat anti collision loop until we can transmit all uid_struct bits + BCC and receive a SAK - max 32 iterations.
|
|
selectDone = false;
|
|
while (!selectDone)
|
|
{
|
|
// Find out how many bits and bytes to send and receive.
|
|
if (current_level_known_bits >= 32)
|
|
{ // All uid_struct bits in this Cascade Level are known. This is a SELECT.
|
|
buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
|
|
// Calculate BCC - Block Check Character
|
|
buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
|
|
// Calculate CRC_A
|
|
result = pcd_calculate_crc(buffer, 7, &buffer[7]);
|
|
if (result != STATUS_OK)
|
|
{
|
|
return result;
|
|
}
|
|
txLastBits = 0; // 0 => All 8 bits are valid.
|
|
bufferUsed = 9;
|
|
// Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
|
|
responseBuffer = &buffer[6];
|
|
responseLength = 3;
|
|
}
|
|
else
|
|
{ // This is an ANTICOLLISION.
|
|
txLastBits = current_level_known_bits % 8;
|
|
count = current_level_known_bits / 8; // Number of whole bytes in the uid_struct part.
|
|
index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
|
|
buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
|
|
bufferUsed = index + (txLastBits ? 1 : 0);
|
|
// Store response in the unused part of buffer
|
|
responseBuffer = &buffer[index];
|
|
responseLength = sizeof(buffer) - index;
|
|
}
|
|
|
|
// Set bit adjustments
|
|
rx_align = txLastBits; // Having a separate variable is overkill. But it makes the next line easier to read.
|
|
write_mfrc522(BitFramingReg, (rx_align << 4) + txLastBits); // rx_align = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
|
|
|
|
// Transmit the buffer and receive the response.
|
|
result = pcd_transceive_data(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rx_align, false);
|
|
if (result == STATUS_COLLISION)
|
|
{ // More than one PICC in the field => collision.
|
|
uint8_t valueOfCollReg = read_mfrc522(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
|
|
if (valueOfCollReg & 0x20)
|
|
{ // CollPosNotValid
|
|
return STATUS_COLLISION; // Without a valid collision position we cannot continue
|
|
}
|
|
uint8_t collisionPos = valueOfCollReg & 0x1F; // Values 0-31, 0 means bit 32.
|
|
if (collisionPos == 0)
|
|
{
|
|
collisionPos = 32;
|
|
}
|
|
if (collisionPos <= current_level_known_bits)
|
|
{ // No progress - should not happen
|
|
return STATUS_INTERNAL_ERROR;
|
|
}
|
|
// Choose the PICC with the bit set.
|
|
current_level_known_bits = collisionPos;
|
|
count = (current_level_known_bits - 1) % 8; // The bit to modify
|
|
index = 1 + (current_level_known_bits / 8) + (count ? 1 : 0); // First byte is index 0.
|
|
buffer[index] |= (1 << count);
|
|
}
|
|
else if (result != STATUS_OK)
|
|
{
|
|
return result;
|
|
}
|
|
else
|
|
{ // STATUS_OK
|
|
if (current_level_known_bits >= 32)
|
|
{ // This was a SELECT.
|
|
selectDone = true; // No more anticollision
|
|
// We continue below outside the while.
|
|
}
|
|
else
|
|
{ // This was an ANTICOLLISION.
|
|
// We now have all 32 bits of the uid_struct in this Cascade Level
|
|
current_level_known_bits = 32;
|
|
// Run loop again to do the SELECT.
|
|
}
|
|
}
|
|
} // End of while (!selectDone)
|
|
|
|
// We do not check the CBB - it was constructed by us above.
|
|
|
|
// Copy the found uid_struct bytes from buffer[] to uid->uidByte[]
|
|
index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
|
|
bytes_to_copy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
|
|
for (count = 0; count < bytes_to_copy; count++)
|
|
{
|
|
uid->uidByte[uid_index + count] = buffer[index++];
|
|
}
|
|
|
|
// Check response SAK (Select Acknowledge)
|
|
if (responseLength != 3 || txLastBits != 0)
|
|
{ // SAK must be exactly 24 bits (1 byte + CRC_A).Select Acknowledge
|
|
return STATUS_ERROR;
|
|
}
|
|
// Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
|
|
result = pcd_calculate_crc(responseBuffer, 1, &buffer[2]);
|
|
if (result != STATUS_OK)
|
|
{
|
|
return result;
|
|
}
|
|
if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
|
|
{
|
|
return STATUS_CRC_WRONG;
|
|
}
|
|
if (responseBuffer[0] & 0x04)
|
|
{ // Cascade bit set - uid_struct not complete yes
|
|
cascadeLevel++;
|
|
}
|
|
else {
|
|
uidComplete = true;
|
|
uid->sak = responseBuffer[0];
|
|
}
|
|
} // End of while (!uidComplete)
|
|
|
|
// Set correct uid->size
|
|
uid->size = 3 * cascadeLevel + 1;
|
|
|
|
return STATUS_OK;
|
|
} // End picc_select()
|
|
|
|
/**
|
|
* Instructs a PICC in state ACTIVE(*) to go to state HALT.
|
|
*
|
|
* @return STATUS_OK on success, STATUS_??? otherwise.
|
|
*/
|
|
status_code
|
|
picc_halt_a()
|
|
{
|
|
status_code result;
|
|
uint8_t buffer[4];
|
|
|
|
// Build command buffer
|
|
buffer[0] = PICC_CMD_HLTA;
|
|
buffer[1] = 0;
|
|
// Calculate CRC_A
|
|
result = pcd_calculate_crc(buffer, 2, &buffer[2]);
|
|
if (result != STATUS_OK)
|
|
{
|
|
return result;
|
|
}
|
|
// Send the command.
|
|
// The standard says:
|
|
// If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
|
|
// HLTA command, this response shall be interpreted as 'not acknowledge'.
|
|
// We interpret that this way: Only STATUS_TIMEOUT is a success.
|
|
result = pcd_transceive_data(buffer, sizeof(buffer), NULL, 0, NULL, 0, false);
|
|
if (result == STATUS_TIMEOUT)
|
|
{
|
|
return STATUS_OK;
|
|
}
|
|
if (result == STATUS_OK)
|
|
{ // That is ironically NOT ok in this case ;-)
|
|
return STATUS_ERROR;
|
|
}
|
|
return result;
|
|
} // End picc_halt_a()
|
|
|
|
/**
|
|
* Returns a __FlashStringHelper pointer to the PICC type name.
|
|
*
|
|
* @return const __FlashStringHelper *
|
|
*/
|
|
void
|
|
picc_get_type_name(picc_type piccType)
|
|
{
|
|
/*switch (piccType)
|
|
{
|
|
case PICC_TYPE_ISO_14443_4: printf("PICC compliant with ISO/IEC 14443-4\n"); break;
|
|
case PICC_TYPE_ISO_18092: printf("PICC compliant with ISO/IEC 18092 (NFC)\n");break;
|
|
case PICC_TYPE_MIFARE_MINI: printf("MIFARE Mini, 320 bytes\n");break;
|
|
case PICC_TYPE_MIFARE_1K: printf("MIFARE 1KB\n");break;
|
|
case PICC_TYPE_MIFARE_4K: printf("MIFARE 4KB\n");break;
|
|
case PICC_TYPE_MIFARE_UL: printf("MIFARE Ultralight or Ultralight C\n");break;
|
|
case PICC_TYPE_MIFARE_PLUS: printf("MIFARE Plus\n");break;
|
|
case PICC_TYPE_MIFARE_DESFIRE: printf("MIFARE DESFire\n");break;
|
|
case PICC_TYPE_TNP3XXX: printf("MIFARE TNP3XXX\n");break;
|
|
case PICC_TYPE_NOT_COMPLETE: printf("SAK indicates uid_struct is not complete.\n");break;
|
|
case PICC_TYPE_UNKNOWN:
|
|
default: printf("Unknown type\n");
|
|
}*/
|
|
} // End picc_get_type_name()
|
|
|
|
|
|
/**
|
|
* Transmits REQA or WUPA commands.
|
|
* Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
|
|
*
|
|
* @return STATUS_OK on success, STATUS_??? otherwise.
|
|
*/
|
|
status_code
|
|
picc_reqa_or_wupa( uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
|
|
{
|
|
uint8_t valid_bits;
|
|
status_code status;
|
|
|
|
if (bufferATQA == NULL || *bufferSize < 2)
|
|
{ // The ATQA response is 2 bytes long.
|
|
//printf("picc_reqa_or_wupa > STATUS_NO_ROOM: %x\n", STATUS_NO_ROOM);
|
|
return STATUS_NO_ROOM;
|
|
}
|
|
|
|
pcd_clear_register_bit_mask(CollReg, 0x80); // ValuesAfterColl=1 => Bits received after collision are cleared.
|
|
valid_bits = 7; // For REQA and WUPA we need the short frame format - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
|
|
status = pcd_transceive_data(&command, 1, bufferATQA, bufferSize, &valid_bits, 0, false);
|
|
if (status != STATUS_OK)
|
|
{
|
|
//printf("picc_reqa_or_wupa > status: %x\n", status);
|
|
return status;
|
|
}
|
|
if (*bufferSize != 2 || valid_bits != 0)
|
|
{ // ATQA must be exactly 16 bits.
|
|
//printf("STATUS_ERROR: %x\n", STATUS_ERROR);
|
|
return STATUS_ERROR;
|
|
}
|
|
return STATUS_OK;
|
|
} // End picc_reqa_or_wupa()
|
|
|
|
|
|
/**
|
|
* Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
|
|
* Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
|
|
*
|
|
* @return STATUS_OK on success, STATUS_??? otherwise.
|
|
*/
|
|
status_code
|
|
picc_request_a( uint8_t *bufferATQA,uint8_t *bufferSize)
|
|
{
|
|
return picc_reqa_or_wupa(PICC_CMD_REQA, bufferATQA, bufferSize);
|
|
} // End picc_request_a()
|
|
|
|
/**
|
|
* Returns true if a PICC responds to PICC_CMD_REQA.
|
|
* Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
|
|
*
|
|
* @return bool
|
|
*/
|
|
bool
|
|
picc_is_new_card_present()
|
|
{
|
|
uint8_t bufferATQA[2];
|
|
uint8_t bufferSize = sizeof(bufferATQA);
|
|
|
|
// Reset baud rates
|
|
write_mfrc522(TxModeReg, 0x00);
|
|
write_mfrc522(RxModeReg, 0x00);
|
|
// Reset ModWidthReg
|
|
write_mfrc522(ModWidthReg, 0x26);
|
|
|
|
|
|
status_code result = picc_request_a(bufferATQA, &bufferSize);
|
|
|
|
return (result == STATUS_OK || result == STATUS_COLLISION);
|
|
} // End picc_is_new_card_present()
|
|
|
|
/**
|
|
* Simple wrapper around picc_select.
|
|
* Returns true if a uid_struct could be read.
|
|
* Remember to call picc_is_new_card_present(), picc_request_a() or PICC_WakeupA() first.
|
|
* The read uid_struct is available in the class variable uid.
|
|
*
|
|
* @return bool
|
|
*/
|
|
bool
|
|
picc_read_card_serial()
|
|
{
|
|
status_code result = picc_select(&uid,0);
|
|
return (result == STATUS_OK);
|
|
} // End
|
|
|
|
status_code
|
|
pcd_authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, uid_struct *uid)
|
|
{
|
|
uint8_t wait_irq = 0x10; // IdleIRq
|
|
uint8_t i;
|
|
// Build command buffer
|
|
uint8_t send_data[12];
|
|
send_data[0] = command;
|
|
send_data[1] = blockAddr;
|
|
for ( i = 0; i < MF_KEY_SIZE; i++)
|
|
{ // 6 key bytes
|
|
send_data[2+i] = key->keyByte[i];
|
|
}
|
|
// Use the last uid_struct bytes as specified in http://cache.nxp.com/documents/application_note/AN10927.pdf
|
|
// section 3.2.5 "MIFARE Classic Authentication".
|
|
// The only missed case is the MF1Sxxxx shortcut activation,
|
|
// but it requires cascade tag (CT) byte, that is not part of uid.
|
|
for ( i = 0; i < 4; i++)
|
|
{ // The last 4 bytes of the UID
|
|
send_data[8+i] = uid->uidByte[i+uid->size-4];
|
|
}
|
|
|
|
// Start the authentication.
|
|
return pcd_communicate_tith_picc(pcd_mf_authent, wait_irq, &send_data[0], sizeof(send_data), NULL, NULL, NULL, 0, false);
|
|
} // End pcd_authenticate()
|
|
|
|
void
|
|
antenna_on()
|
|
{
|
|
uint8_t value ;
|
|
value = read_mfrc522(TxControlReg);
|
|
if ((value & 0x03) != 0x03) {
|
|
write_mfrc522(TxControlReg, value | 0x03);
|
|
}
|
|
value = read_mfrc522(TxControlReg);
|
|
}
|
|
|
|
/*
|
|
* Initializes the MFRC522 chip.
|
|
*/
|
|
bool
|
|
pcd_initialization()
|
|
{
|
|
//printf("pcd_initialization()\n");
|
|
|
|
mfr_reset_down();
|
|
us_delay_spi(2);
|
|
mfr_reset_up();
|
|
|
|
us_delay_spi(50000);
|
|
|
|
pcd_reset();
|
|
|
|
// Reset baud rates
|
|
write_mfrc522(TxModeReg, 0x00);
|
|
write_mfrc522(RxModeReg, 0xb0);
|
|
//Reset ModWidthReg
|
|
write_mfrc522(ModWidthReg, 0x26);
|
|
// When communicating with a PICC we need a timeout if something goes wrong.
|
|
// f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
|
|
// TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
|
|
write_mfrc522(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
|
|
write_mfrc522(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25μs.
|
|
write_mfrc522(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
|
|
write_mfrc522(TReloadRegL, 0xE8);
|
|
write_mfrc522(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
|
|
write_mfrc522(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
|
|
write_mfrc522(RFCfgReg,0x70);
|
|
write_mfrc522(ComIEnReg,0x80);
|
|
write_mfrc522(FIFOLevelReg,0x00);
|
|
antenna_on(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
|
|
|
|
//printf("initialization Done()\n");
|
|
|
|
return 1;
|
|
} // End pcd_initialization() */
|
|
|
|
|
|
|
|
|