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237 lines
13 KiB
C
237 lines
13 KiB
C
#ifndef _RFID_SPI_H_
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#define _RFID_SPI_H_
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#include <includes.h>
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#include "spi.h"
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#include <stdint.h>
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#include <stdbool.h>
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#define SPI_CS 0x01 //PC0
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#define SPI_MOSI 0x10 //PA4
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#define SPI_MISO 0x02 //PB1
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#define SPI_Ck 0x04 //PA2
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#define GPIO_PIN_6 0x40 //SDA (SLAVE SELECT)
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#define MAX_LEN 16 // Maximum length of the array
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#define MI_OK 0
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#define MI_NOTAGERR 1
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#define MI_ERR 2
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#define PICC_REQIDL 0x26 // Area of the antenna is not trying to get into the idle state
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#define Reserved00 0x00
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#define CommIEnReg 0x02
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#define DivlEnReg 0x03
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#define CommIrqReg 0x04
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#define PCD_IDLE 0x00 // No action; And cancel the command
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#define PCD_AUTHENT 0x0E // authentication key
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#define PCD_RECEIVE 0x08 // receiving data
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#define PCD_TRANSMIT 0x04 // Send data
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#define PCD_TRANSCEIVE 0x0C // Send and receive data
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#define PCD_RESETPHASE 0x0F // reset
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#define PCD_CALCCRC 0x03 // calculate CRC
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#define Reserved01 0x0F
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//Page 1:Command
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#define Reserved10 0x10
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#define Reserved11 0x1A
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#define Reserved12 0x1B
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#define MifareReg 0x1C
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#define Reserved13 0x1D
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#define Reserved14 0x1E
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//Page 2:CFG
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#define Reserved20 0x20
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#define Reserved21 0x23
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#define CRCResultRegM 0x21 // shows the MSB and LSB values of the CRC calculation
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// MFRC522 commands. Described in chapter 10 of the datasheet.
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#define PCD_Idle 0x00 // no action, cancels current command execution
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#define PCD_Mem 0x01 // stores 25 bytes into the internal buffer
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#define PCD_GenerateRandomID 0x02 // generates a 10-byte random ID number
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#define PCD_CalcCRC 0x03 // activates the CRC coprocessor or performs a self test
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#define PCD_Transmit 0x04 // transmits data from the FIFO buffer
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#define PCD_NoCmdChange 0x07 // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
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#define PCD_Receive 0x08 // activates the receiver circuits
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#define PCD_Transceive 0x0C // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
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#define pcd_mf_authent 0x0E // performs the MIFARE standard authentication as a reader
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#define PCD_SoftReset 0x0F // resets the MFRC522
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#define TxAutoReg 0x15
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#define delay_ms(i) (ti_lib_cpu_delay(8000 * (i)))
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typedef enum {
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// Page 0: Command and status
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// 0x00 // reserved for future use
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CommandReg = 0x01 , // starts and stops command execution
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ComIEnReg = 0x02 , // enable and disable interrupt request control bits
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DivIEnReg = 0x03 , // enable and disable interrupt request control bits
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ComIrqReg = 0x04 , // interrupt request bits
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DivIrqReg = 0x05 , // interrupt request bits
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ErrorReg = 0x06 , // error bits showing the error status of the last command executed
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Status1Reg = 0x07 , // communication status bits
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Status2Reg = 0x08 , // receiver and transmitter status bits
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FIFODataReg = 0x09 , // input and output of 64 byte FIFO buffer
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FIFOLevelReg = 0x0A , // number of bytes stored in the FIFO buffer
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WaterLevelReg = 0x0B , // level for FIFO underflow and overflow warning
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ControlReg = 0x0C , // miscellaneous control registers
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BitFramingReg = 0x0D , // adjustments for bit-oriented frames
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CollReg = 0x0E , // bit position of the first bit-collision detected on the RF interface
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// 0x0F // reserved for future use
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// Page 1: Command
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// 0x10 // reserved for future use
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ModeReg = 0x11 , // defines general modes for transmitting and receiving
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TxModeReg = 0x12 , // defines transmission data rate and framing
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RxModeReg = 0x13 , // defines reception data rate and framing
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TxControlReg = 0x14 , // controls the logical behavior of the antenna driver pins TX1 and TX2
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TxASKReg = 0x15 , // controls the setting of the transmission modulation
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TxSelReg = 0x16 , // selects the internal sources for the antenna driver
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RxSelReg = 0x17 , // selects internal receiver settings
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RxThresholdReg = 0x18 , // selects thresholds for the bit decoder
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DemodReg = 0x19 , // defines demodulator settings
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// 0x1A // reserved for future use
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// 0x1B // reserved for future use
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MfTxReg = 0x1C , // controls some MIFARE communication transmit parameters
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MfRxReg = 0x1D , // controls some MIFARE communication receive parameters
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// 0x1E // reserved for future use
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SerialSpeedReg = 0x1F , // selects the speed of the serial UART interface
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// Page 2: Configuration
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// 0x20 // reserved for future use
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CRCResultRegH = 0x21 , // shows the MSB and LSB values of the CRC calculation
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CRCResultRegL = 0x22 ,
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// 0x23 // reserved for future use
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ModWidthReg = 0x24 , // controls the ModWidth setting?
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// 0x25 // reserved for future use
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RFCfgReg = 0x26 , // configures the receiver gain
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GsNReg = 0x27 , // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
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CWGsPReg = 0x28 , // defines the conductance of the p-driver output during periods of no modulation
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ModGsPReg = 0x29 , // defines the conductance of the p-driver output during periods of modulation
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TModeReg = 0x2A , // defines settings for the internal timer
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TPrescalerReg = 0x2B , // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
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TReloadRegH = 0x2C , // defines the 16-bit timer reload value
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TReloadRegL = 0x2D ,
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TCounterValueRegH = 0x2E , // shows the 16-bit timer value
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TCounterValueRegL = 0x2F ,
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// Page 3: Test Registers
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// 0x30 // reserved for future use
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TestSel1Reg = 0x31 , // general test signal configuration
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TestSel2Reg = 0x32 , // general test signal configuration
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TestPinEnReg = 0x33 , // enables pin output driver on pins D1 to D7
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TestPinValueReg = 0x34 , // defines the values for D1 to D7 when it is used as an I/O bus
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TestBusReg = 0x35 , // shows the status of the internal test bus
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AutoTestReg = 0x36 , // controls the digital self-test
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VersionReg = 0x37 , // shows the software version
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AnalogTestReg = 0x38 , // controls the pins AUX1 and AUX2
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TestDAC1Reg = 0x39 , // defines the test value for TestDAC1
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TestDAC2Reg = 0x3A , // defines the test value for TestDAC2
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TestADCReg = 0x3B // shows the value of ADC I and Q channels
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// 0x3C // reserved for production tests
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// 0x3D // reserved for production tests
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// 0x3E // reserved for production tests
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// 0x3F // reserved for production tests
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}pcd_register;
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// Commands sent to the PICC.
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typedef enum {
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// The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
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PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
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PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
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PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
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PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
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PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 2
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PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 3
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PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
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PICC_CMD_RATS = 0xE0, // Request command for Answer To Reset.
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// The commands used for MIFARE Classic (from http://www.mouser.com/ds/2/302/MF1S503x-89574.pdf, Section 9)
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// Use pcd_mf_authent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
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// The read/write commands can also be used for MIFARE Ultralight.
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PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
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PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
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PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
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PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
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PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
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PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
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PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
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PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
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// The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
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// The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
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PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
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}PICC_Command;
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typedef enum {
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PICC_TYPE_UNKNOWN ,
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PICC_TYPE_ISO_14443_4 , // PICC compliant with ISO/IEC 14443-4
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PICC_TYPE_ISO_18092 , // PICC compliant with ISO/IEC 18092 (NFC)
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PICC_TYPE_MIFARE_MINI , // MIFARE Classic protocol, 320 bytes
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PICC_TYPE_MIFARE_1K , // MIFARE Classic protocol, 1KB
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PICC_TYPE_MIFARE_4K , // MIFARE Classic protocol, 4KB
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PICC_TYPE_MIFARE_UL , // MIFARE Ultralight or Ultralight C
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PICC_TYPE_MIFARE_PLUS , // MIFARE Plus
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PICC_TYPE_MIFARE_DESFIRE, // MIFARE DESFire
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PICC_TYPE_TNP3XXX , // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
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PICC_TYPE_NOT_COMPLETE = 0xff // SAK indicates uid_struct is not complete.
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}picc_type;
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// Return codes from the functions in this class. Remember to update Getstatus_codeName() if you add more.
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// last value set to 0xff, then compiler uses less ram, it seems some optimisations are triggered
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typedef enum {
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STATUS_OK , // Success
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STATUS_ERROR , // Error in communication
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STATUS_COLLISION , // Collission detected
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STATUS_TIMEOUT , // Timeout in communication.
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STATUS_NO_ROOM , // A buffer is not big enough.
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STATUS_INTERNAL_ERROR , // Internal error in the code. Should not happen ;-)
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STATUS_INVALID , // Invalid argument.
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STATUS_CRC_WRONG , // The CRC_A does not match
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STATUS_MIFARE_NACK = 0xff // A MIFARE PICC responded with NAK.
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}status_code;
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typedef enum {
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MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
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MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
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}MIFARE_Misc;
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// A struct used for passing a MIFARE Crypto1 key
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typedef struct {
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uint8_t keyByte[MF_KEY_SIZE];
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} MIFARE_Key;
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// A struct used for passing the uid_struct of a PICC.
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typedef struct {
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uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
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uint8_t uidByte[10];
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uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
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} uid_struct;
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void write_bytes_mfrc522( pcd_register reg, uint8_t count, uint8_t *values);
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void write_mfrc522(uint8_t adr, uint8_t val);
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uint8_t read_mfrc522(uint8_t dev_cmd);
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void read_fifo_mfrc522( pcd_register reg, uint8_t count, uint8_t *values, uint8_t rx_align);
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picc_type picc_get_type(uint8_t sak);
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void pcd_set_register_bit_mask(pcd_register reg, uint8_t mask);
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status_code pcd_calculate_crc(uint8_t *data, uint8_t length, uint8_t *result);
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void pcd_reset();
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status_code pcd_communicate_tith_picc(uint8_t command, uint8_t wait_irq, uint8_t *send_data, uint8_t send_len, uint8_t *back_data, uint8_t *back_len, uint8_t *valid_bits, uint8_t rx_align, bool check_crc);
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status_code pcd_transceive_data(uint8_t *send_data, uint8_t send_len, uint8_t *back_data, uint8_t *back_len, uint8_t *valid_bits, uint8_t rx_align, bool check_crc);
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status_code mifare_read( uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
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status_code mifare_write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
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void pcd_clear_register_bit_mask(pcd_register reg, uint8_t mask);
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void pcd_stop_cryptol();
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status_code picc_select( uid_struct *uid, uint8_t valid_bits);
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status_code picc_halt_a();
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void picc_get_type_name(picc_type piccType);
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status_code picc_reqa_or_wupa( uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
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status_code picc_request_a( uint8_t *bufferATQA,uint8_t *bufferSize);
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bool picc_is_new_card_present();
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bool picc_read_card_serial();
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status_code pcd_authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, uid_struct *uid);
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void get_status_code_name (status_code code);
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void antenna_on();
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bool pcd_initialization();
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uid_struct * get_uid();
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#endif |