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259 lines
17 KiB
C
259 lines
17 KiB
C
/*
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*********************************************************************************************************
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* uC/TCP-IP
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* The Embedded TCP/IP Suite
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*
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* (c) Copyright 2003-2006; Micrium, Inc.; Weston, FL
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*
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* All rights reserved. Protected by international copyright laws.
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*
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* uC/TCP-IP is provided in source form for FREE evaluation, for educational
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* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
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* product you need to contact Micrium to properly license its use in your
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* product. We provide ALL the source code for your convenience and to help
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* you experience uC/TCP-IP. The fact that the source code is provided does
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* NOT mean that you can use it without paying a licensing fee.
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*
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* Network Interface Card (NIC) port files provided, as is, for FREE and do
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* NOT require any additional licensing or licensing fee.
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*
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* Knowledge of the source code may NOT be used to develop a similar product.
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*
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* Please help us continue to provide the Embedded community with the finest
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* software available. Your honesty is greatly appreciated.
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* NETWORK PHYSICAL LAYER
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*
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* National DP83848
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*
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* Filename : net_phy.c
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* Version : V1.89
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* Programmer(s) : EHS
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*********************************************************************************************************
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* Note(s) : (1) Supports National Semiconductor DP83848 10/100 PHY
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*
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* (2) The MII interface port is assumed to be part of the host EMAC; consequently,
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* reads from and writes to the PHY are made through the EMAC. The functions
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* NetNIC_PhyRegRd() and NetNIC_PhyRegWr(), which are used to access the PHY, should
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* be provided in the EMAC driver.
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*********************************************************************************************************
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*/
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#ifndef _NET_PHY_H
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#define _NET_PHY_H
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/*
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*********************************************************************************************************
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* DEFINES
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*********************************************************************************************************
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*/
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#define DP83848_INIT_AUTO_NEG_RETRIES 3 /* Attempt Auto-Negotiation 3 times */
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#define DP83848_INIT_RESET_RETRIES 16 /* Check for successful reset 8 times */
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#define DP83848_OUI 0x080017
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#define DP83848_VNDR_MDL 0x09
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/*
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*********************************************************************************************************
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* DP83848 REGISTER DEFINES
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*********************************************************************************************************
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*/
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/* ------- Generic MII registers ---------- */
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#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_ANAR 0x04 /* Advertisement control reg */
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#define MII_ANLPAR 0x05 /* Link partner ability reg */
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#define MII_ANER 0x06 /* Expansion register */
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#define MII_ANNPTR 0x07 /* Next page transmit register */
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/* --------- Extended registers ----------- */
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#define DP83848_PHYSTS 0x10 /* PHY Status Register */
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#define DP83848_MICR 0x11 /* MII Interrupt Control Register */
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#define DP83848_MISR 0x12 /* MII Interrupt Status/Misc. Control Reg. */
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#define DP83848_FCSCR 0x14 /* False Carrier Sense Counter Register */
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#define DP83848_RECR 0x15 /* Receiver Error Counter Register */
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#define DP83848_PCSR 0x16 /* 100 Mb/s PCS Config. & Status Register */
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#define DP83848_RBR 0x17 /* RMII and Bypass Register */
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#define DP83848_LEDCR 0x18 /* LED Direct Control Register */
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#define DP83848_PHYCR 0x19 /* PHY Control Register */
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#define DP83848_10BTSCR 0x1A /* 10Base-T Status/Control Register */
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#define DP83848_CDCTRL1 0x1B /* CD Test & BIST Extensions Register */
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#define DP83848_EDCR 0x1D /* Energy Detect Control */
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/*
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*********************************************************************************************************
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* DP83848 REGISTER BITS
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*********************************************************************************************************
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*/
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/* -------- MII_BMCR Register Bits -------- */
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#define BMCR_RESV 0x007F /* Unused... */
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#define BMCR_CTST DEF_BIT_07 /* Collision test */
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#define BMCR_FULLDPLX DEF_BIT_08 /* Full duplex */
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#define BMCR_ANRESTART DEF_BIT_09 /* Auto negotiation restart */
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#define BMCR_ISOLATE DEF_BIT_10 /* Disconnect DP83840 from MII */
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#define BMCR_PDOWN DEF_BIT_11 /* Powerdown the DP83840 */
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#define BMCR_ANENABLE DEF_BIT_12 /* Enable auto negotiation */
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#define BMCR_SPEED100 DEF_BIT_13 /* Select 100Mbps */
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#define BMCR_LOOPBACK DEF_BIT_14 /* TXD loopback bits */
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#define BMCR_RESET DEF_BIT_15 /* Reset the DP83840 */
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/* -------- MII_BMSR Register Bits -------- */
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#define BMSR_ERCAP DEF_BIT_00 /* Ext-reg capability */
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#define BMSR_JCD DEF_BIT_01 /* Jabber detected */
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#define BMSR_LSTATUS DEF_BIT_02 /* Link status */
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#define BMSR_ANEGCAPABLE DEF_BIT_03 /* Able to do auto-negotiation */
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#define BMSR_RFAULT DEF_BIT_04 /* Remote fault detected */
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#define BMSR_ANEGCOMPLETE DEF_BIT_05 /* Auto-negotiation complete */
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#define BMSR_RESV 0x07C0 /* Unused... */
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#define BMSR_10HALF DEF_BIT_11 /* Can do 10mbps, half-duplex */
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#define BMSR_10FULL DEF_BIT_12 /* Can do 10mbps, full-duplex */
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#define BMSR_100HALF DEF_BIT_13 /* Can do 100mbps, half-duplex */
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#define BMSR_100FULL DEF_BIT_14 /* Can do 100mbps, full-duplex */
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#define BMSR_100BASE4 DEF_BIT_15 /* Can do 100mbps, 4k packets */
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/* -------- MII_ANAR Register Bits -------- */
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#define ANAR_SLCT 0x001F /* Selector bits */
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#define ANAR_CSMA DEF_BIT_04 /* Only selector supported */
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#define ANAR_10HALF DEF_BIT_05 /* Try for 10mbps half-duplex */
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#define ANAR_10FULL DEF_BIT_06 /* Try for 10mbps full-duplex */
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#define ANAR_100HALF DEF_BIT_07 /* Try for 100mbps half-duplex */
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#define ANAR_100FULL DEF_BIT_08 /* Try for 100mbps full-duplex */
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#define ANAR_100BASE4 DEF_BIT_09 /* Try for 100mbps 4k packets */
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#define ANAR_RESV 0x1C00 /* Unused... */
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#define ANAR_RFAULT DEF_BIT_13 /* Say we can detect faults */
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#define ANAR_LPACK DEF_BIT_14 /* Ack link partners response */
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#define ANAR_NPAGE DEF_BIT_15 /* Next page bit */
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#define ANAR_FULL (ANAR_100FULL | ANAR_10FULL | ANAR_CSMA)
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#define ANAR_ALL (ANAR_100FULL | ANAR_10FULL | ANAR_100HALF | ANAR_10HALF)
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/* ------- MII_ANLPAR Register Bits ------- */
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#define ANLPAR_SLCT 0x001F /* Same as advertise selector */
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#define ANLPAR_10HALF DEF_BIT_05 /* Can do 10mbps half-duplex */
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#define ANLPAR_10FULL DEF_BIT_06 /* Can do 10mbps full-duplex */
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#define ANLPAR_100HALF DEF_BIT_07 /* Can do 100mbps half-duplex */
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#define ANLPAR_100FULL DEF_BIT_08 /* Can do 100mbps full-duplex */
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#define ANLPAR_100BASE4 DEF_BIT_09 /* Can do 100mbps 4k packets */
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#define ANLPAR_RESV 0x1C00 /* Unused... */
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#define ANLPAR_RFAULT DEF_BIT_13 /* Link partner faulted */
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#define ANLPAR_LPACK DEF_BIT_14 /* Link partner acked us */
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#define ANLPAR_NPAGE DEF_BIT_15 /* Next page bit */
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#define ANLPAR_DUPLEX (ANLPAR_10FULL | ANLPAR_100FULL)
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#define ANLPAR_100 (ANLPAR_100FULL | ANLPAR_100HALF | ANLPAR_100BASE4)
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/* -------- MII_ANER Register Bits -------- */
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#define ANER_NWAY DEF_BIT_00 /* Can do N-way auto-nego */
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#define ANER_LCWP DEF_BIT_01 /* Got new RX page code word */
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#define ANER_ENABLENPAGE DEF_BIT_02 /* This enables npage words */
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#define ANER_NPCAPABLE DEF_BIT_03 /* Link partner supports npage */
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#define ANER_MFAULTS DEF_BIT_04 /* Multiple faults detected */
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#define ANER_RESV 0xFFE0 /* Unused... */
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/* ----- DP83848_PHYSTS Register Bits ----- */
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#define PHYSTS_LINK_STATUS DEF_BIT_00
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#define PHYSTS_SPEED_STATUS DEF_BIT_01
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#define PHYSTS_DUPLEX_STATUS DEF_BIT_02
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#define PHYSTS_LOOPBACK_STATUS DEF_BIT_03
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#define PHYSTS_AN_COMPLETE DEF_BIT_04
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#define PHYSTS_JABBER_DETECT DEF_BIT_05
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#define PHYSTS_REMOTE_FAULT DEF_BIT_06
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#define PHYSTS_MII_INTERRUPT DEF_BIT_07
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#define PHYSTS_PAGE_RCVD DEF_BIT_08
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#define PHYSTS_DESCRAMBLER_LOCK DEF_BIT_09
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#define PHYSTS_SIGNAL_DETECT DEF_BIT_10
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#define PHYSTS_FALSE_CARRIER_SENSE DEF_BIT_11
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#define PHYSTS_POLARITY_STATUS DEF_BIT_12
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#define PHYSTS_RECEIVE_ERROR_LATCH DEF_BIT_13
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#define PHYSTS_MDIX_MODE DEF_BIT_14
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/*
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*********************************************************************************************************
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* PHY ERROR CODES 12,000 -> 13,000
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*********************************************************************************************************
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*/
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#define NET_PHY_ERR_NONE 12000
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#define NET_PHY_ERR_REGRD_TIMEOUT 12010
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#define NET_PHY_ERR_REGWR_TIMEOUT 12020
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#define NET_PHY_ERR_AUTONEG_TIMEOUT 12030
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#define NET_PHY_ERR_RESET_TIMEOUT 12040
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/*
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*********************************************************************************************************
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* FUNCTION PROTOTYPES
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*********************************************************************************************************
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*/
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void NetNIC_PhyInit (NET_ERR *perr);
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void NetNIC_PhyAutoNeg (void); /* Do link auto-negotiation */
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/* -----------------PHY STATUS FNCTS ------------------ */
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CPU_BOOLEAN NetNIC_PhyAutoNegState (void); /* Get PHY auto-negotiation state */
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CPU_BOOLEAN NetNIC_PhyLinkState (void); /* Get PHY link state */
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CPU_INT32U NetNIC_PhyLinkSpeed (void); /* Get PHY link speed */
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CPU_INT32U NetNIC_PhyLinkDuplex (void); /* Get PHY duplex mode */
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/*
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*********************************************************************************************************
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* FUNCTION PROTOTYPES
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* DEFINED IN PRODUCT'S net_bsp.c
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*********************************************************************************************************
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*/
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void NetNIC_LinkUp (void); /* Message from NIC that the ethernet link is up. */
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/* Called in interruption context most of the time. */
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void NetNIC_LinkDown (void); /* Message from NIC that the ethernet link is down. */
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/* Called in interruption context most of the time. */
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/*
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*********************************************************************************************************
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* CONFIGURATION ERRORS
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*********************************************************************************************************
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*/
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#ifndef NET_NIC_CFG_INT_CTRL_EN
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#error "NET_NIC_CFG_INT_CTRL_EN not #define'd in 'net_cfg.h'"
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#error " [MUST be DEF_DISABLED] "
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#error " [ || DEF_ENABLED ] "
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#elif ((NET_NIC_CFG_INT_CTRL_EN != DEF_DISABLED) && \
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(NET_NIC_CFG_INT_CTRL_EN != DEF_ENABLED ))
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#error "NET_NIC_CFG_INT_CTRL_EN illegally #define'd in 'net_cfg.h'"
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#error " [MUST be DEF_DISABLED] "
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#error " [ || DEF_ENABLED ] "
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#endif
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#ifndef EMAC_CFG_PHY_ADDR
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#error "EMAC_CFG_PHY_ADDR not #define'd in 'net_bsp.h'"
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#endif
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#ifndef EMAC_CFG_RMII
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#error "EMAC_CFG_RMII not #define'd in 'net_bsp.h'"
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#error " [MUST be DEF_YES ]"
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#error " [ || DEF_NO ]"
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#elif ((EMAC_CFG_RMII != DEF_YES) && \
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(EMAC_CFG_RMII != DEF_NO ))
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#error "EMAC_CFG_RMII illegally #define'd in 'net_bsp.h'"
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#error " [MUST be DEF_YES]"
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#error " [ || DEF_NO ]"
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#endif
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#endif
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