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This commit is contained in:
Dmitriy 2024-09-03 22:49:51 +03:00
parent e983dee285
commit 6f35400812
4 changed files with 9 additions and 14 deletions
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2
OS/app/app_cfg.h
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@ -30,7 +30,7 @@
********************************************************************************************************* *********************************************************************************************************
*/ */
#define APP_TASK_START_STK_SIZE 128 #define APP_TASK_START_STK_SIZE 256
#define NET_OS_CFG_TMR_TASK_STK_SIZE 300 #define NET_OS_CFG_TMR_TASK_STK_SIZE 300
#define NET_OS_CFG_IF_RX_TASK_STK_SIZE 640 #define NET_OS_CFG_IF_RX_TASK_STK_SIZE 640
#define APP_TASK_PHY_STK_SIZE 640 #define APP_TASK_PHY_STK_SIZE 640

13
OS/bsp/LPC2368_Flash.icf
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@ -5,9 +5,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000044; define symbol __ICFEDIT_region_ROM_start__ = 0x00000044;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007CFFF; define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_CONFIG_start__ = 0x0007D000;
define symbol __ICFEDIT_region_CONFIG_end__ = 0x0007DFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x40000000; define symbol __ICFEDIT_region_RAM_start__ = 0x40000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x40007FFF; define symbol __ICFEDIT_region_RAM_end__ = 0x40007FFF;
/*-Sizes-*/ /*-Sizes-*/
@ -17,14 +15,13 @@ define symbol __ICFEDIT_size_irqstack__ = 0x100;
define symbol __ICFEDIT_size_fiqstack__ = 0x40; define symbol __ICFEDIT_size_fiqstack__ = 0x40;
define symbol __ICFEDIT_size_undstack__ = 0x10; define symbol __ICFEDIT_size_undstack__ = 0x10;
define symbol __ICFEDIT_size_abtstack__ = 0x10; define symbol __ICFEDIT_size_abtstack__ = 0x10;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G; define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region CONFIG_region = mem:[from __ICFEDIT_region_CONFIG_start__ to __ICFEDIT_region_CONFIG_end__];
define symbol __region_USB_DMA_RAM_start__ = 0x7FD00000; define symbol __region_USB_DMA_RAM_start__ = 0x7FD00000;
define symbol __region_USB_DMA_RAM_end__ = 0x7FD01FFF; define symbol __region_USB_DMA_RAM_end__ = 0x7FD01FFF;
/*define region USB_DMA_RAM_region= mem:[from __region_USB_DMA_RAM_start__ to __region_USB_DMA_RAM_end__];*/ /*define region USB_DMA_RAM_region= mem:[from __region_USB_DMA_RAM_start__ to __region_USB_DMA_RAM_end__];*/
@ -42,6 +39,7 @@ define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit }; do not initialize { section .noinit };
@ -51,12 +49,9 @@ do not initialize { section EMAC_DMA_RAM };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in CONFIG_region { readonly section .config};
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK}; block UND_STACK, block ABT_STACK, block HEAP };
/*place in USB_DMA_RAM_region*/ /*place in USB_DMA_RAM_region*/
/* { readwrite data section USB_DMA_RAM };*/ /* { readwrite data section USB_DMA_RAM };*/
place in EMAC_DMA_RAM_region place in EMAC_DMA_RAM_region

4
OS/bsp/bsp.c
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@ -464,9 +464,9 @@ static void PLL_Init (void)
PLLFEED = 0x55; PLLFEED = 0x55;
CPU_CRITICAL_EXIT(); CPU_CRITICAL_EXIT();
SCS |= DEF_BIT_00; /* enable fast IO */
SCS &= ~DEF_BIT_04; /* OSCRANGE = 0, Main OSC is between 1 and 20 Mhz */ SCS &= ~DEF_BIT_04; /* OSCRANGE = 0, Main OSC is between 1 and 20 Mhz */
SCS |= DEF_BIT_05; /* OSCEN = 1, Enable the main oscillator */ SCS |= DEF_BIT_05; /* OSCEN = 1, Enable the main oscillator */
SCS |= DEF_BIT_00; /* access to all ports as fast io */
while ((SCS & DEF_BIT_06) == 0) { /* Wait until OSCSTAT is set (Main OSC ready to be used) */ while ((SCS & DEF_BIT_06) == 0) { /* Wait until OSCSTAT is set (Main OSC ready to be used) */
; ;
@ -564,7 +564,7 @@ static void GPIO_Init (void)
{ {
IO0DIR = 0; IO0DIR = 0;
IO1DIR = 0; IO1DIR = 0;
FIO0DIR = 0x1000000; // õîïïåð óæå íàñòðîèëè FIO0DIR = 0;
FIO1DIR = 0; FIO1DIR = 0;
FIO2DIR = 0; FIO2DIR = 0;
FIO3DIR = 0; FIO3DIR = 0;

2
settings/sk-mlpc2368.Flash_Central.general.xcl
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@ -2,7 +2,7 @@
"C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armJLINK.dll" "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armJLINK.dll"
"C:\git_work\changer\Flash Central\Exe\version0_14.out" "C:\git_work\changer\Flash Central\Exe\version0_31.out"
--plugin="C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armbat.dll" --plugin="C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armbat.dll"