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240 lines
10 KiB
C
240 lines
10 KiB
C
/*
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*********************************************************************************************************
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* uC/TCP-IP
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* The Embedded TCP/IP Suite
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*
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* (c) Copyright 2003-2006; Micrium, Inc.; Weston, FL
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*
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* All rights reserved. Protected by international copyright laws.
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*
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* uC/TCP-IP is provided in source form for FREE evaluation, for educational
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* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
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* product you need to contact Micrium to properly license its use in your
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* product. We provide ALL the source code for your convenience and to help
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* you experience uC/TCP-IP. The fact that the source code is provided does
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* NOT mean that you can use it without paying a licensing fee.
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*
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* Network Interface Card (NIC) port files provided, as is, for FREE and do
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* NOT require any additional licensing or licensing fee.
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*
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* Knowledge of the source code may NOT be used to develop a similar product.
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*
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* Please help us continue to provide the Embedded community with the finest
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* software available. Your honesty is greatly appreciated.
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* NETWORK PHYSICAL LAYER
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*
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* National DP83848
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*
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* Filename : net_phy.c
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* Version : V1.89
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* Programmer(s) : EHS
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*********************************************************************************************************
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* Note(s) : (1) Supports National Semiconductor DP83848 10/100 PHY
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*
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* (2) The MII interface port is assumed to be part of the host EMAC; consequently,
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* reads from and writes to the PHY are made through the EMAC. The functions
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* NetNIC_PhyRegRd() and NetNIC_PhyRegWr(), which are used to access the PHY, should
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* be provided in the EMAC driver.
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*********************************************************************************************************
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*/
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#ifndef _NET_PHY_H
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#define _NET_PHY_H
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/*
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*********************************************************************************************************
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* DEFINES
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*********************************************************************************************************
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*/
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#define DP83848_INIT_AUTO_NEG_RETRIES 3 /* Attempt Auto-Negotiation 3 times */
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#define DP83848_INIT_RESET_RETRIES 16 /* Check for successful reset 8 times */
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#define DP83848_OUI 0x080017
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#define DP83848_VNDR_MDL 0x09
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/*
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*********************************************************************************************************
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* DP83848 REGISTER DEFINES
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*********************************************************************************************************
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*/
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/* ------- Generic MII registers ---------- */
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#define PHY_BMCR 0x0000
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#define PHY_BMSR 0x0001
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#define PHY_PHYIDR1 0x0002
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#define PHY_PHYIDR2 0x0003
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#define PHY_ANAR 0x0004
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#define PHY_ANLPAR 0x0005
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#define PHY_ANLPARNP 0x0005
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#define PHY_ANER 0x0006
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#define PHY_ANNPTR 0x0007
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#define PHY_LPNPA 0x0008
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#define PHY_RECR 0x0015
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#define PHY_INTCTRL 0x001B
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#define PHY_100PHY 0x001F
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/*
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*********************************************************************************************************
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* DP83848 REGISTER BITS
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*********************************************************************************************************
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*/
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/* -------- MII_BMCR Register Bits -------- */
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/* BMCR bitmap */
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#define BMCR_RESET 0x8000
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#define BMCR_LOOPBACK 0x4000
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#define BMCR_SPEED_100 0x2000
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#define BMCR_AN 0x1000
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#define BMCR_POWERDOWN 0x0800
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#define BMCR_ISOLATE 0x0400
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#define BMCR_RE_AN 0x0200
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#define BMCR_DUPLEX 0x0100
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/* BMSR bitmap */
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#define BMSR_100BE_T4 0x8000
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#define BMSR_100TX_FULL 0x4000
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#define BMSR_100TX_HALF 0x2000
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#define BMSR_10BE_FULL 0x1000
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#define BMSR_10BE_HALF 0x0800
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#define BMSR_NOPREAM 0x0040
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#define BMSR_AUTO_DONE 0x0020
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#define BMSR_REMOTE_FAULT 0x0010
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#define BMSR_NO_AUTO 0x0008
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#define BMSR_LINK_ESTABLISHED 0x0004
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/* PHY_ANAR bitmap */
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#define ANAR_NEXT_PAGE 0x8000
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#define ANAR_REMOTE_FAULT 0x2000
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#define ANAR_PAUSE 0x0400
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#define ANAR_100BE_T4 0x0200
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#define ANAR_100BT_FULL 0x0100
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#define ANAR_100BT 0x0080
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#define ANAR_10BT_FULL 0x0040
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#define ANAR_10BT 0x0020
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#define ANAR_SELECTOR 0x001F
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/* ANLPAR bitmap */
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#define ANLPAR_NEXT_PAGE 0x8000
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#define ANLPAR_ACKN 0x4000
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#define ANLPAR_REMOTE_FAULT 0x2000
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#define ANLPAR_PAUSE 0x0C00
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#define ANLPAR_100BE_T4 0x0200
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#define ANLPAR_100BT_FULL 0x0100
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#define ANLPAR_100BT 0x0080
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#define ANLPAR_10BT_FULL 0x0040
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#define ANLPAR_10BT 0x0020
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#define ANLPAR_SELECTOR 0x001F
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/* PHY_100PHY setting */
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#define PHYCR_MDIX_DIS 0x2000
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#define PHYCR_ENR_DET 0x1000
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#define PHYCR_FORCE_LINK 0x0800
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#define PHYCR_POWER_SAVING 0x0400
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#define PHYCR_INTR_LEVEL 0x0200
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#define PHYCR_JABBER_ENA 0x0100
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#define PHYCR_PAUSE_ENA 0x0080
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#define PHYCR_PHY_ISO 0x0040
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#define PHYCR_MODE 0x001C
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#define PHYCR_SQE_TST_ENA 0x0002
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#define PHYCR_SCRAM_DIS 0x0001
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/* MAC PHY address */
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#define MAC_PHY_ADDR 1
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/* Set these bits in eth->req_speed prior to starting driver */
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#define LINKSTAT_SPEED_10 0x1
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#define LINKSTAT_SPEED_10_FD 0x2
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#define LINKSTAT_SPEED_100 0x4
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#define LINKSTAT_SPEED_100_FD 0x8
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#define LINKSTAT_LINKDOWN 0x8000
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#define LINKSTAT_AUTO_NEGOTIATE 0x4000
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/*
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*********************************************************************************************************
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* PHY ERROR CODES 12,000 -> 13,000
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*********************************************************************************************************
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*/
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#define NET_PHY_ERR_NONE 12000
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#define NET_PHY_ERR_REGRD_TIMEOUT 12010
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#define NET_PHY_ERR_REGWR_TIMEOUT 12020
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#define NET_PHY_ERR_AUTONEG_TIMEOUT 12030
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#define NET_PHY_ERR_RESET_TIMEOUT 12040
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/*
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*********************************************************************************************************
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* FUNCTION PROTOTYPES
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*********************************************************************************************************
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*/
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extern void NetNIC_PhyInit (NET_ERR *perr);
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extern void NetNIC_PhyAutoNeg (void); /* Do link auto-negotiation */
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/* -----------------PHY STATUS FNCTS ------------------ */
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extern CPU_BOOLEAN NetNIC_PhyAutoNegState (void); /* Get PHY auto-negotiation state */
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extern CPU_BOOLEAN NetNIC_PhyLinkState (void); /* Get PHY link state */
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extern CPU_INT32U NetNIC_PhyLinkSpeed (void); /* Get PHY link speed */
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extern CPU_INT32U NetNIC_PhyLinkDuplex (void); /* Get PHY duplex mode */
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/*
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*********************************************************************************************************
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* FUNCTION PROTOTYPES
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* DEFINED IN PRODUCT'S net_bsp.c
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*********************************************************************************************************
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*/
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void NetNIC_LinkUp (void); /* Message from NIC that the ethernet link is up. */
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/* Called in interruption context most of the time. */
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void NetNIC_LinkDown (void); /* Message from NIC that the ethernet link is down. */
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/* Called in interruption context most of the time. */
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/*
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*********************************************************************************************************
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* CONFIGURATION ERRORS
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*********************************************************************************************************
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*/
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#ifndef NET_NIC_CFG_INT_CTRL_EN
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#error "NET_NIC_CFG_INT_CTRL_EN not #define'd in 'net_cfg.h'"
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#error " [MUST be DEF_DISABLED] "
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#error " [ || DEF_ENABLED ] "
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#elif ((NET_NIC_CFG_INT_CTRL_EN != DEF_DISABLED) && \
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(NET_NIC_CFG_INT_CTRL_EN != DEF_ENABLED ))
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#error "NET_NIC_CFG_INT_CTRL_EN illegally #define'd in 'net_cfg.h'"
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#error " [MUST be DEF_DISABLED] "
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#error " [ || DEF_ENABLED ] "
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#endif
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#ifndef EMAC_CFG_PHY_ADDR
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#error "EMAC_CFG_PHY_ADDR not #define'd in 'net_bsp.h'"
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#endif
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#ifndef EMAC_CFG_RMII
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#error "EMAC_CFG_RMII not #define'd in 'net_bsp.h'"
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#error " [MUST be DEF_YES ]"
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#error " [ || DEF_NO ]"
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#elif ((EMAC_CFG_RMII != DEF_YES) && \
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(EMAC_CFG_RMII != DEF_NO ))
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#error "EMAC_CFG_RMII illegally #define'd in 'net_bsp.h'"
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#error " [MUST be DEF_YES]"
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#error " [ || DEF_NO ]"
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#endif
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#endif
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