mirror of
https://github.com/dimoniche/Moyka.git
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133 lines
5.6 KiB
ArmAsm
133 lines
5.6 KiB
ArmAsm
;
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;********************************************************************************************************
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; EXCEPTION VECTORS & STARTUP CODE
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;
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; File : cstartup.s
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; For : ARM7 or ARM9
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; Toolchain : IAR EWARM V5.10 and higher
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;********************************************************************************************************
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;
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;********************************************************************************************************
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; MACROS AND DEFINIITIONS
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;********************************************************************************************************
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; Mode, correspords to bits 0-5 in CPSR
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MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
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USR_MODE DEFINE 0x10 ; User mode
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FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
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IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
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SVC_MODE DEFINE 0x13 ; Supervisor mode
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ABT_MODE DEFINE 0x17 ; Abort mode
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UND_MODE DEFINE 0x1B ; Undefined Instruction mode
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SYS_MODE DEFINE 0x1F ; System mode
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;********************************************************************************************************
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; ARM EXCEPTION VECTORS
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;********************************************************************************************************
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SECTION .intvec:CODE:NOROOT(2)
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PUBLIC __vector
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PUBLIC __iar_program_start
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PUBLIC __vector_0x14
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IMPORT OS_CPU_ARM_ExceptUndefInstrHndlr
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IMPORT OS_CPU_ARM_ExceptSwiHndlr
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IMPORT OS_CPU_ARM_ExceptPrefetchAbortHndlr
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IMPORT OS_CPU_ARM_ExceptDataAbortHndlr
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IMPORT OS_CPU_ARM_ExceptIrqHndlr
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IMPORT OS_CPU_ARM_ExceptFiqHndlr
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ARM
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__vector:
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LDR PC, [PC,#24] ; Absolute jump can reach 4 GByte
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LDR PC, [PC,#24] ; Branch to undef_handler
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LDR PC, [PC,#24] ; Branch to swi_handler
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LDR PC, [PC,#24] ; Branch to prefetch_handler
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LDR PC, [PC,#24] ; Branch to data_handler
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__vector_0x14:
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DC32 0 ; Reserved
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LDR PC, [PC,#24] ; Branch to irq_handler
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LDR PC, [PC,#24] ; Branch to fiq_handler
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DC32 __iar_program_start
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DC32 OS_CPU_ARM_ExceptUndefInstrHndlr
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DC32 OS_CPU_ARM_ExceptSwiHndlr
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DC32 OS_CPU_ARM_ExceptPrefetchAbortHndlr
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DC32 OS_CPU_ARM_ExceptDataAbortHndlr
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DC32 0
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DC32 OS_CPU_ARM_ExceptIrqHndlr
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DC32 OS_CPU_ARM_ExceptFiqHndlr
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;********************************************************************************************************
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; LOW-LEVEL INITIALIZATION
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;********************************************************************************************************
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION text:CODE:NOROOT(2)
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REQUIRE __vector
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EXTERN ?main
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PUBLIC __iar_program_start
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EXTERN lowlevel_init
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__iar_program_start:
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;********************************************************************************************************
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; STACK POINTER INITIALIZATION
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;********************************************************************************************************
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MRS r0,cpsr ; Original PSR value
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BIC r0,r0,#MODE_BITS ; Clear the mode bits
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ORR r0,r0,#SVC_MODE ; Set SVC mode bits
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MSR cpsr_c,r0 ; Change the mode
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LDR sp,=SFE(SVC_STACK) ; End of SVC_STACK
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BIC r0,r0,#MODE_BITS ; Clear the mode bits
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ORR r0,r0,#UND_MODE ; Set UND mode bits
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MSR cpsr_c,r0 ; Change the mode
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LDR sp,=SFE(UND_STACK) ; End of UND_STACK
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BIC r0,r0,#MODE_BITS ; Clear the mode bits
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ORR r0,r0,#ABT_MODE ; Set ABT mode bits
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MSR cpsr_c,r0 ; Change the mode
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LDR sp,=SFE(ABT_STACK) ; End of ABT_STACK
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BIC r0,r0,#MODE_BITS ; Clear the mode bits
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ORR r0,r0,#FIQ_MODE ; Set FIQ mode bits
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MSR cpsr_c,r0 ; Change the mode
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LDR sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
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BIC r0,r0,#MODE_BITS ; Clear the mode bits
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ORR r0,r0,#IRQ_MODE ; Set IRQ mode bits
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MSR cpsr_c,r0 ; Change the mode
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LDR sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
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BIC r0,r0,#MODE_BITS ; Clear the mode bits
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ORR r0,r0,#SYS_MODE ; Set System mode bits
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MSR cpsr_c,r0 ; Change the mode
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LDR sp,=SFE(CSTACK) ; End of CSTACK
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;********************************************************************************************************
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; ADDITIONAL INITIALIZATION
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;********************************************************************************************************
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;********************************************************************************************************
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; CONTINUE TO ?main FOR ADDITIONAL INITIALIZATION
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;********************************************************************************************************
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LDR r0,=?main
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BX r0
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END
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